1. The Field of the Invention
The present invention relates to circuits and methods for amplifying electrical signals. More specifically, the present invention relates to circuits and methods for performing amplification by charge transfer without using a reference voltage.
2. The Prior State of the Art
There are many circuits and methods conventionally available for amplifying an electrical signal. One type of amplifier is called a charge transfer amplifier. Charge transfer amplifiers operate on the principle of capacitive charge sharing. Voltage amplification is achieved by transferring a specific amount of charge between appropriately sized capacitors through an active device.
FIG. 1 illustrates a charge transfer amplifier 100 that utilizes an NMOS transistor MN1 to transfer charge between capacitors CT and CO. The operation of the NMOS charge transfer amplifier 100 will now be described in order to illustrate the basic principle of charge transfer amplification.
The NMOS charge transfer amplifier 100 operates on an amplifier cycle involving three phases including a reset phase, a precharge phase, and an amplify phase. FIG. 2 is a signal timing diagram for two input signals S1 and S2 with respect to the phase that the NMOS charge transfer amplifier 100 is operating in whether that phase be (a) the reset phase, (b) the precharge phase or (c) the amplify phase. The two input signals S1 and S2 control corresponding switches /S1 and /S2 of FIG. 1. FIG. 2 also shows a clock signal CLK. It is apparent that each amplifier cycle takes two complete clock cycles. The reset and precharge phases each take a half clock cycle, and the amplify phase takes a full clock cycle.
Throughout this application, signal S1 controls switch S1 (not yet described) and switch /S1, and signal S2 controls switch S2 (not yet described) and switch /S2. Although signal S3 is not yet described and is not used in conventional charge transfer amplifiers, signal S3 controls switch S3 (not yet described). The slash symbol xe2x80x9c/xe2x80x9d in the value of a switch indicates that the switch is closed when the corresponding control signal is low, and open when the corresponding control signal is high. Conversely, the absence of a slash symbol xe2x80x9c/xe2x80x9d in the value of a switch indicates that the switch is open when the corresponding control signal is low, and closed when the corresponding control signal is high. Similar nomenclature is used throughout this application for all the switches illustrated and/or described herein.
The cycle begins with the (a) reset phase in which the signal S1 is low indicating that the switch /S1 is closed, and in which the signal S2 is low indicating that the switch /S2 is closed. Since the switch /S1 is closed, the upper terminal of capacitor CT (i.e., node 101) is discharged through the switch /S1 to voltage Vss. Switch /S2 is closed indicating that the upper terminal of capacitor CO (i.e., node 102) is forced to a precharge reference voltage VPR.
After the reset phase is the (b) precharge phase in which the signal S1 is high indicating that switch /S1 is open, and in which the signal S2 is low indicating that the switch /S2 remains closed. Thus, the upper terminal of the capacitor CO (i.e., node 102) remains charged to the precharge reference voltage VPR. This precharge reference voltage VPR is high enough that current flows from node 102 to the capacitor CT (and node 101) through the NMOS transistor MN1. For example, if the precharge reference voltage VPR is at least equal to the input voltage VIN at the gate of the NMOS transistor MN1, then the discharge continues until the voltage at the capacitor CT increases to be equal to the input voltage VIN minus the threshold voltage (hereinafter xe2x80x9cVTNxe2x80x9d) of the NMOS transistor MN1. At that point, the NMOS transistor MN1 enters the cutoff region and current flow to the capacitor CT substantially ceases. Thus, at the end of the precharge phase, the capacitor CO ideally has a voltage of VPR while the capacitor CT has a voltage of VINxe2x88x92VTN.
After the precharge phase is the (c) amplify phase in which both signals S1 and S2 are high indicating that both switches /S1 and /S2 are open. During the amplify phase, an incrementally positive input voltage change xcex94VIN applied at the gate of the NMOS transistor MN1 will cause the NMOS transistor MN1 to turn on thereby allowing current to flow through the NMOS transistor MN1 until the NMOS transistor MN1 is again cutoff. For small incrementally positive voltage changes xcex94VIN, the NMOS transistor MN1 will cutoff when the voltage on the upper terminal of the capacitor CT (i.e., node 101) increases by the incrementally positive voltage change xcex94VIN. The amount of charge transferred to the capacitor CT in order to produce this effect is equal to the incrementally positive voltage change xcex94VIN times the capacitance CT of the capacitor CT.
Since the charge xcex94VINxc3x97CT transferred to the capacitor CT came from node 102 through transistor MN1, the charge xcex94VINxc3x97CT was drawn from the capacitor CO. Thus, the voltage at the capacitor CO and the output voltage VOUT will change by xcex94VINxc3x97(CT/C0). If the capacitance CT is greater than the capacitance C0, amplification occurs.
One advantage of the NMOS charge transfer amplifier 100 is that the voltage gain and power consumption may be controlled by setting the capacitance of the capacitors CO and CT as well as by setting the capacitance ratio CT/C0.
Another advantage of charge transfer amplifiers in general is that the circuit performance is generally unaffected by the absolute values of the supply voltage Vss and Vdd as long as these voltages permit proper biasing during the reset and precharge phases. In other words, charge transfer amplifiers have high supply voltage scalability in that no changes are needed for a charge transfer amplifier to operate using a wide range of supply voltages Vss and Vdd. Although the NMOS charge transfer amplifier 100 has these advantages, there are at least two disadvantages to amplifying using the NMOS charge transfer amplifier 100.
First, amplification only occurs if the input gate voltage change xcex94VIN is positive. A negative gate voltage change xcex94VIN would only cause the NMOS transistor MN1 to enter deeper into the cutoff region. Thus, charge transfer between node A and node B would be stifled thereby preventing amplification.
Second, leakage currents inherent in transistor MN1 will alter the expected zero-bias (i.e., no input signal) conditions on capacitors CT and CO during the amplify phase. This leakage current may be caused by current undesirably leaking from the source/drain diffusion regions of the NMOS transistor MN1 into the substrate in which they are formed. Leakage current may also be caused by current flowing between the source and drain terminals of the NMOS transistor MN1 even though the NMOS transistor MN1 is substantially cutoff. Either way, this leakage current effectively produces a voltage error at the output terminal that introduces amplification error.
FIG. 3 shows a conventional CMOS charge transfer amplifier 300 that substantially overcomes the above-described limitations of the NMOS charge transfer amplifier 100. The CMOS charge transfer amplifier 300 includes an NMOS charge transfer amplifier 301 that is similar to the NMOS charge transfer amplifier 100 described above, except that a switch S1 is provided between the source of the NMOS transistor MN1 and the charge transfer capacitor CTL. This inhibits leakage current in the NMOS transistor MN1 during the reset phase.
For clarity, the NMOS charge transfer amplifier 301 is shown in FIG. 3 as being enclosed by a dotted box. The CMOS charge transfer amplifier 300 also includes a partially overlapping PMOS charge transfer amplifier 302 which is shown in FIG. 3 enclosed by a dashed box for clarity. The PMOS charge transfer amplifier 302 shares the voltage input line 303, the voltage output line 304 and the precharge line 305 with the NMOS charge transfer amplifier 301.
The PMOS charge transfer amplifier 302 is structured similar to the NMOS charge transfer amplifier 301 except that the PMOS charge transfer amplifier 302 uses a PMOS transistor MP1 instead of an NMOS transistor MN1 for transferring charge between capacitors. Also, node 201 of the PMOS charge transfer amplifier 302 is reset to a high voltage Vdd instead of the low voltage Vss and is capacitively coupled to the high voltage Vdd instead of the low voltage Vss.
The general operation of the PMOS charge transfer amplifier 302 for negative input voltage changes xcex94VIN is similar to the operation of the NMOS charge transfer amplifier 301 for positive voltage changes xcex94VIN. Thus, the input signals S1 and S2 of FIG. 2 are used in the operation of the CMOS charge transfer amplifier 300. Due to the complementary nature of the NMOS charge transfer amplifier 301 and the PMOS charge transfer amplifier 302, the CMOS charge transfer amplifier 300 amplifies for both positive and negative input voltage changes xcex94VIN thereby overcoming one of the two described limitations of the NMOS charge transfer amplifier 100. Furthermore, the effect of the leakage current may be minimized by sizing the NMOS transistor MN1 and the PMOS transistor MP1 so that the leakage currents match closely. While the match is never perfect or even predictable, the overall voltage error is usually lowered relative to the voltage error of the NMOS charge transfer amplifier 100 alone.
As apparent from FIG. 3, there are five different voltages involved with the CMOS charge transfer amplifier 300. The input voltage VIN and the output voltage VOUT are, of course, inherent to the operation of an amplifier. The supply voltages Vdd and Vss are readily available to the circuit as a whole. Thus, there is very little cost in making these supply voltages available to the CMOS charge transfer amplifier 300. The precharge reference voltage VPR is also conventionally part of the charge transfer amplifier and is conventionally provided at a mid-supply level approximately midway between the supply voltages Vdd and Vss.
Conventional charge transfer amplifiers use the precharge reference voltage VPR for at least two good reasons. First, by supplying the precharge reference voltage VPR at mid-supply between Vdd and Vss, the output voltage VOUT is also precharged to mid-supply during the precharge phase. During the amplify phase, xcex94VIN causes the output voltage VOUT to change slightly. However, the output voltage VOUT is still generally centered at mid-supply. This is important for circuitry subsequent to the CMOS charge transfer amplifier 300. Such subsequent circuitry may include, for example, a dynamic latch comparator or another amplifier, and will typically have a limited range of allowable input voltage levels. An input voltage centered at mid-supply is typically within that limited range of allowable input voltage levels for subsequent circuitry.
The second good reason for using a mid-supply precharge reference voltage VPR is that this ensures proper self-biasing of the transistors MN1 and MP1 of the CMOS charge transfer amplifier 300 during the precharge and amplify phases. For these two reasons, the use of a precharge reference voltage VPR is standard in conventional charge transfer amplifiers.
Generating a voltage such as VPR that differs from the supply voltages Vdd and Vss poses logistical problems for many types of circuits. Generating the precharge reference voltage VPR off-chip may increase the overall size of the amplifier package. Generating the precharge reference voltage on-chip consumes valuable die real estate. Whether implemented on-chip or off-chip, the generation of the precharge reference voltage VPR, results in Direct Current (or xe2x80x9cDCxe2x80x9d) power dissipation and some degree of design complexity.
Accordingly, what is desired are circuits and methods for performing charge transfer amplification without using a precharge reference voltage VPR.
The foregoing problems in the prior state of the art have been successfully overcome by the present invention, which is directed to circuits and methods performing charge transfer amplification without using a precharge reference voltage.
The charge transfer amplifier has a first supply voltage source (e.g., Vdd) and a second supply voltage source (e.g., Vss) that has a lower voltage than the first supply voltage source. The charge transfer amplifier also includes a PMOS transistor and an NMOS transistor that share a common gate terminal that is coupled to the input terminal. The charge transfer amplifier further includes a first input capacitor CTU capacitively coupling a first node (e.g., node A of FIG. 4) to a fixed voltage, a second input capacitor CTL capacitively coupling a second node (e.g., node B) to a fixed voltage, a first intermediate capacitor CRU capacitively coupling the output terminal to the drain of the PMOS transistor (e.g., node DP), and a second intermediate capacitor CRL capacitively coupling the output terminal to the drain of the NMOS transistor (e.g., node DN).
The charge transfer amplifier has an amplification cycle that includes a reset phase, a precharge phase, and an amplify phase. During the reset phase, a relatively fixed voltage (VREF) is applied to the input terminal of the charge transfer amplifier. Node A is reset to Vdd, and node B, node DP, node DN, and the output terminal are reset to Vss. Optionally, node A is isolated from the source of the PMOS transistor, and node B is isolated from the source of the NMOS transistor during the reset phase to thereby reduce or prevent leakage current.
During the precharge phase, node A is disconnected from Vdd and connected to the source of the PMOS transistor. Node B is disconnected from Vss and connected to the source of the NMOS transistor. Node DN is coupled to Vdd. This result in charge from node A passing through the PMOS transistor and to the node DP until the voltage at node A equals the gate voltage minus the threshold voltage of the PMOS transistor, at which point the PMOS transistor becomes cutoff. Also, charge from node DN passes through the NMOS transistor and to the node B until the voltage at node B equals the gate voltage minus the threshold voltage of the NMOS transistor, at which point the NMOS transistor becomes cutoff.
During the amplify phase, an incremental voltage change is applied to the common gate terminal. Also the drain of the PMOS transistor is disconnected from Vss, and the drain of the NMOS transistor is disconnected from Vdd. For positive incremental voltage changes, the NMOS transistor temporarily exits the cutoff region and conducts charge from node DN to node B. This results in a voltage decrease at the output terminal that is proportional to the positive incremental voltage change. For negative incremental voltage changes, the PMOS transistor temporarily exits the cutoff region and conducts charge from node A to node DP. This result in a voltage increase at the output terminal that is proportional to the negative incremental voltage change.
The charge transfer amplification is performed without a precharge reference voltage. Accordingly, the increased package size due to on-chip implementation of the precharge reference voltage and/or the use of the die space occupied by the precharge reference voltage source may be avoided thus resulting in a more compact charge transfer amplifier.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.